基于忆阻器边缘计算的图像分类电路设计
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四川大学锦江学院

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V221.3

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国家自然科学基金项目(面上项目,重点项目,重大项目)


Design of Image Classification Circuit Based on Edge Computing of Memristor
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Sichuan University Jinjiang College,

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    摘要:

    本文针对边缘智能设备低功耗,轻算力的要求,采用了新型存算一体器件-忆阻器作为基础电路元件,设计了低功耗、图像别电路。该电路采用多个忆阻卷积层和忆阻全连接网络串联的方式,获得了较高的识别精度。为了减小忆阻卷积层计算所需的忆阻交叉阵列的行尺寸和列尺寸的不平衡,同时降低输入电压方向电路的功耗,将输入电压反相器置于忆阻交叉阵列之后。该电路可以将完成忆阻卷积网络运算所需的忆阻交叉阵列的行大小从2M+1减少到M+1,同时将单个卷积核计算所需的反相器的数量降低到了1,从而大幅度降低了忆阻卷积网络的体积和功耗。利用数学近似,将BN层和dropout层计算合并到CNN层中,减小网络层数同时降低电路的功耗。通过在CIFAR-10数据集上的实验表明,该电路可以有效地对图像进行分类,同时具备推理速度快(187ns)和功耗低的优点(单个神经元功耗小于3.5uW)。

    Abstract:

    Aiming at the requirements of low power consumption and light computing power for edge smart devices, this paper uses a new type of integrated storage and computing device-memristor as the basic circuit element, and designs low power consumption and image-specific circuits. The circuit uses a series of multiple memristive convolutional layers and a memristive fully connected network to obtain high recognition accuracy. In order to reduce the imbalance of the row size and column size of the memristive interleaved array required for calculation of the memristive convolutional layer, and at the same time reduce the power consumption of the input voltage direction circuit, the input voltage inverter is placed after the memristive interleaved array. This circuit can reduce the row size of the memristive interleaved array required to complete the memristive convolution network operation from 2M+1 to M+1, and at the same time reduce the number of inverters required for the calculation of a single convolution core to 1, This greatly reduces the volume and power consumption of the memristive convolutional network. Using mathematical approximation, the calculations of the BN layer and the dropout layer are merged into the CNN layer to reduce the number of network layers and reduce the power consumption of the circuit. Experiments on the CIFAR-10 data set show that the circuit can effectively classify images, while having the advantages of fast inference speed (187ns) and low power consumption (the power consumption of a single neuron is less than 3.5uW).

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  • 收稿日期:2021-01-21
  • 最后修改日期:2021-06-22
  • 录用日期:2021-07-05
  • 在线发布日期: 2021-08-01
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